JTAG

JTAG (Joint Test Action Group) is a standard dedicated to electronics system automated testing.
It allows to test all chips that have JTAG functionality with a single test connector. To allow this, all JTAG devices are daisy chained like on the picture below. In reality, there is often one JTAG connector per device because debug tools do not always support chain.

Signals

Following signals are used for JTAG :

• TMS, (Test Mode Select) Signal to enable JTAG communication
• TCK, (Test ClocK) Clock signal
• TDI, (Test Data Input) Data Input
• TDO, (Test Data Output) Data Output
• TRST, (Test ReSeT) Optional, allows to reset JTAG Controller, Active low

Following signals are optional :

• RTCK, (Returned Test Clock) Optional signal, allows to adjust JTAG clock depending on the target
• NRST, (“Neutral Test Reset) Target reset, often connected to System reset

Connectors

Multiple connectors versions exists depending on debug tools. Most commons are the following

ARM 20 pins

ARM 14 pins

MIPS EJTAG

Altera Byteblaster 10 pins

AVR 10 pins